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NXP Semiconductors /LPC408x_7x /TIMER0 /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE)CAP0RE 0 (DISABLE)CAP0FE 0 (DISABLE)CAP0I 0 (DISABLE)CAP1RE 0 (DISABLE)CAP1FE 0 (DISABLE)CAP1I 0RESERVED

CAP0I=DISABLE, CAP0RE=DISABLE, CAP1I=DISABLE, CAP0FE=DISABLE, CAP1RE=DISABLE, CAP1FE=DISABLE

Description

Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Fields

CAP0RE

Capture on CAPn.0 rising edge

0 (DISABLE): This feature is disabled.

1 (ENABLE): A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
CAP0FE

Capture on CAPn.0 falling edge

0 (DISABLE): This feature is disabled.

1 (ENABLE): A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
CAP0I

Interrupt on CAPn.0 event

0 (DISABLE): This feature is disabled.

1 (ENABLE): A CR0 load due to a CAPn.0 event will generate an interrupt.
CAP1RE

Capture on CAPn.1 rising edge

0 (DISABLE): This feature is disabled.

1 (ENABLE): A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
CAP1FE

Capture on CAPn.1 falling edge

0 (DISABLE): This feature is disabled.

1 (ENABLE): A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
CAP1I

Interrupt on CAPn.1 event

0 (DISABLE): This feature is disabled.

1 (ENABLE): A CR1 load due to a CAPn.1 event will generate an interrupt.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data